The present invention relates to a semiconductor device having a clock and data recovery circuit.
A clock and data recovery (CDR) circuit that recovers a clock signal and a data signal from a received data is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2005-5999, No. 2006-80991, and No. 2011-234009.
For example, as illustrated in FIG. 25, a serdes (serializer/deserializer) that mutually convert serial data and parallel data includes pairs (one or plural pairs of) of transmitter circuits 43 and receiver circuits 41, and a PLL (phase locked loop) 30. One PLL 30 is connected with one or more of the transmitter circuits 43 and one or more of the receiver circuits 41.
Each of the receiver circuits 41 includes a clock and data recovery circuit 50 that receives serial data and a PLL clock signal from the PLL 30, and extracts a clock signal synchronous with the serial data, and a serial/parallel converter circuit 42 that converts the serial data into parallel data with the use of the serial data and the clock signal which are extracted by the clock and data recovery circuit 50. Each of the transmitter circuits 43 includes a parallel/serial converter circuit 44 that receives the parallel data, and converts and outputs the parallel data into serial data on the basis of the PLL clock signal.
In a serdes interface, the clock and data recovery circuit 50 receives the serial data that has been subjected to spread-spectrum frequency modulation, and extracts the clock signal (clock signal modulated by the spread-spectrum frequency modulation) synchronous with the serial data.
An SSC (spread spectrum clocking) clock signal which is subjected to the spread-spectrum frequency modulation is input to the clock and data recovery circuit 50 as the clock signal. The SSC clock signal adds a dither to a clock frequency to reduce an electro-magnetic interference (EMI). An SSC clock generator device that generates the SSC clock signal is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2006-166049. Also, a PLL having an SSC controller is disclosed in Japanese Unexamined Patent Application Publication No. 2010-283830. The PLL 30 in FIG. 25 includes the SSC controller, and outputs the SSC clock signal.
Each of the transmitter circuits 43 receives the PLL clock signal (SSC clock signal subjected to the spread-spectrum frequency modulation) from the PLL 30, and conducts parallel/serial conversion on the basis of the PLL clock signal, to thereby output the serial data that has been subjected to the spread-spectrum frequency modulation.
Each of the receiver circuits 41 receives the PLL clock signal (SSC clock signal subjected to the spread-spectrum frequency modulation) from the PLL 30, and data (subjected to the spread-spectrum frequency modulation) from a transmitter circuit (not shown) of a counter serdes, and extracts the clock signal and the data in the clock and data recovery circuit 50.
The clock and data recovery circuit 50 samples a serial data input and outputs extracted data according to an extracted clock signal, and the serial/parallel converter circuit 42 converts the extracted serial data into parallel data with the use of the extracted clock, and outputs a parallel data output to a downstream circuit.
When the serial data input and the PLL clock signal are each subjected to the spread-spectrum frequency modulation, the clock and data recovery circuit 50 needs to follow not only a phase difference of the data and the clock, but also a frequency deviation.
FIG. 26 is a diagram based on FIG. 1 of Japanese Unexamined Patent Application Publication No. 2005-5999. Referring to FIG. 26, in the clock and data recovery circuit 50, a phase detection unit 51 receives the serial data input and the extracted clock signal (extracted clock output by the clock and data recovery circuit 50); detects a retard or an advance of the phase with the result of sampling the serial data according to the extracted clock signal as the extracted data, and outputs a control signal UP1/DOWN1 (up1/down1) indicative of a phase comparison result.
An integrator 14 integrates the control signal UP1/DOWN1 from the phase detection unit 51, and outputs a control signal UPDOWN2.
An integrator 13 integrates the control signal UP1/DOWN1 from the phase detection unit 51, and outputs a control signal UPDOWN3.
A pattern generator 15 receives the control signal UPDOWN3 from the integrator 13, and outputs a control signal UPDOWN4.
A mixer 16 receives the control signal UPDOWN2 from the integrator 14 and the control signal UPDOWN4 from the pattern generator 15, and outputs a control signal UPDOWN5.
A phase interpolator 17 interpolates a phase of the input PLL clock signal (clock signal subjected to the spread-spectrum frequency modulation) on the basis of the control signal UPDOWN5 from the mixer 16. The extracted clock signal output from the phase interpolator 17 is fed back to the phase detection unit 51.
As illustrated in FIG. 26, the clock and data recovery circuit 50 is equipped with a phase tracking loop and a frequency tracking loop. In a spread spectrum clocking (SSC) system, the serial data input and the clock signal, which are input to the clock and data recovery circuit 50, are each swept in frequency, and the frequency deviation is always changed momentarily.
In the frequency tracking loop, a frequency deviation between the serial data input subjected to the spread-spectrum frequency modulation and the clock signal subjected to the spread-spectrum frequency modulation is detected to conduct a feedback control so that a frequency of the extracted clock signal tracks a frequency of the serial data input.